Altera & Intilop announce 40G & 25G Full TCP & UDP Offload Engine for Arria 10 FPGAs. Intilop’s accelerators will be demoed at Supercomputing 2015 in Austin TX.
Another industry first: The 8th Generation TCP & UDP Accelerator series, now running at 40G/25G with Ultra-Low Latency, is a wider extension of their most mature and widely adapted 10G TCP & UDP Acceleration technology solutions across various classes of networking equipment worldwide.
Milpitas, CA., November 10th, 2015— Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators like Full TCP, UDP, IGMP & other Mega IP Cores, Systems and Solutions since 2009, delivers yet another industry first: a full TCP and UDP Accelerator with the native design running at 40G & 25G bps implementing 512 TCP and UDP sessions in Altera Arria10 FPGAs. A live demo will be conducted in booth #462 on Nov. 17th – Nov 19th, 2015 at the Supercomputing 2015 Conference in Austin, TX.
“It was a highly significant achievement to develop a brand new architecture which implements actual 40G & 25G Full TCP and UDP Acceleration utilizing Altera’s latest PCS/MAC technology which use 25G SERDES. We used our experience of developing 7 generations of full TCP and UDP Acceleration over last 7 years. The user-friendly features in Altera’s Quartus Prime V15.1 software allowed us to implement logic very efficiently and run it at full speed without much difficulty. The Mega IP complex takes full advantage of the architectural features in the Arria 10 FPGA. TCP & UDP exhibit around 100 nanosecond latency with highest performance and bandwidth. Our previous Gen Sx-Series10G TOE/UOE also achieved a record breaking latency of sub 100 ns on Stratix V FPGAs across all 16384 Sessions,” said K Masood, President and CTO of Intilop
“Intilop’s 40G & 25G TCP and UDP Acceleration and low latency implementation on an Arria 10 FPGA provides an industry- leading solution for data center customers. This functionality can also be coupled with other FPGA value add functions such as encryption, compression, or virtualization offload for additional benefits.” said Mike Strickland, Director, Data Center Architect for Altera.
Working out of the box solutions with Choice of Cores implementing 1K, 512, 256, 128, 32 and fewer concurrent TCP/UDP Sessions and IGMP V3/V2/v1 will be available in Q1 2016.
Latency of less than 100 nanoseconds for the 8th Gen TOE and UOE at 40G and 25G sets the bar much higher for speed and performance based upon a mature, proven and TCP Protocol Compliant architecture. It not only offers ~100 ns latency and near wire speed TCP performance, it also offers customization flexibility to network architects to design world-class system-level applications tailored to their specific needs.
The TOE’s architecture is highly scalable, customizable and adaptable without compromising on low latency or performance. Intilop’s product-line solutions are available in flexible FPGA/ASIC/SoC technologies which can easily accommodate diverse set of appliance maker’s technical design specifications.
As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Their sub 100 ns latency MAC+TOE&UOE are considered a ‘Gold Standard’ by the industry experts. The latency barrier of 100 nanoseconds and throughput of more than 1 G byte/s per port had been set by them since their first 10G Series of TCP engines in 2011. Now the same performance metrics are provided across all thousand simultaneous TCP Sessions.
About Intilop: Intilop is a developer, provider, a recognized leader and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems.
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Intilop Corporation. 830 N Hillview Drive. Milpitas, CA 95035. PH: 408-791-6700