Intilop’s Methodology is geared towards minimizing verification cycles and costly design respins. Whether designs are targeted towards complex SoC, ASIC, FPGA-SoC or a smaller FPGA, the right methodology is critical to the ultimate success of the project. They can assess the project’s need from several perspectives ranging from Specifications, through architecture, through, micro-architecture through various verification stages all the way up to full system/software validation and recommend an appropriate methodology. In order for our customers to realize a greater cost savings in an already expensive ASIC/SoC project, a significant value-add to customers is the identification and recommendation of the right methodology, tasks and tools particularly required for the project which are essential, pragmatic, proven and cost effective. During a development/verification project, they can stay involve at the execution level as team member, consultant, project manager/coordinator or any role that adds value to our customers.