- 10/100/1000 Mbit, Tri-speed Ethernet MAC with generic host side interface targeted for Xilinx, Altera FPGAs or ASIC design flow
- 802.3x compliant
- Sustained max packet transfer rate at 1G on Tx/Rx side
- 64 - 1500 Byte packets at min IFG
- Programmable Rx FIFOs up to 256 K Byte
- Programmable TX FIFOs up to 256 K bytes
- Programmable MAC address filters
- Statistics Counters
- 10/100 M bit MAC with generic host side interfaces targeted for Xilinx, Altera FPGAs or ASIC design flow
- 802.3x compliant
- Programmable MAC address filters
- TCP/IP hardware accelerator engine for 10/100/1000 Mbit Ethernet MAC targeted for Xilinx, Altera FPGAs or ASIC design flow
- Decode TCP header and commands, compute TCP checksum
- Decode I/P header and command, compute IP checksum
- Direct interface to packet buffers
- Programmable Rx FIFOs
- Programmable TX FIFOs
- System I/O-Bus interfaces-FPGA/ASIC
- USB-2.0 USB-1.1 interface
- SCSI-x, Serial ATA design/Integration
- Custom bus interface design
- All applicable firmware/driver development
- 100G TCP-UDP Value Prop Brochure (Target Specs)
- 40G-1K Sess. TCP + UDP Offload Engine
- 25G-1K Sess. TCP + UDP Offload Engine
- 10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
The following intellectual property cores are available for integration into your designs. The cores are verified and ready to go. Customization and integration services, if desired, are available from Intilop at Intilop standard rates
GIGA BIT ETHERNET MAC
TRI-SPEED ETHERNET MAC
MULTI-GIGA BIT MULTI PORT CROSS POINT SWITCH
USB 2.0 CONTROLLER
USB 1.1 CONTROLLER
PCIX-PCIX BRIDGE
VITERBI DECODER
1024 POINT FFT CORE
DDR1 / DDR2 SDRAM CONTROLLER
PCI SDRAM CONTROLLER
ETHERNET-RF BRIDGE CONTROLLER
SINGLE CHANNEL HDLC CONTROLLER
PCI TO PCI BRIDGE
UART 16450 COMPATIBLE MACRO
UART 16550 COMPATIBLE MACRO